page 1 of 7 document no. 70-0037-05 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. parameter conditions minimum typical maximum units operating frequency 1 dc 3000 mhz insertion loss 1000 mhz 2000 mhz 0.30 0.45 0.40 0.60 db db isolation ? rfc to rf1/rf2 1000 mhz 2000 mhz 34.5 24.5 35.5 25 db db isolation ? rf1 to rf2 1000 mhz 2000 mhz 36.5 25.5 37.5 26.5 db db return loss 1000 mhz 2000 mhz 22.5 15 24.5 16 db db ?on? switching time ctrl to 0.1 db final value, 2 ghz 200 ns ?off? switching time ctrl to 25 db isolation, 2 ghz 90 ns video feedthrough 2 2.5 mv pp input 1 db compression 2000 mhz 13 14.5 dbm input ip3 2000 mhz, 5 dbm 30 33.5 dbm 8-lead msop rfc rf1 rf2 cmos control driver ctrl the PE4210 ultracmos? rf switch is designed to cover a broad range of applications from near dc to 3000 mhz. this single-supply switch integrates on-board cmos control logic driven by a simple, single-pin cmos or ttl compatible control input. using a nominal +3-volt power supply, a typical input 1 db compression point of +14 dbm can be achieved. the PE4210 also exhibits input-output isolation of better than 35 db at 1000 mhz and is offered in a small 8-lead msop package. the PE4210 ultracmos? rf switch is manufactured in peregrine?s patented ultra thin silicon (utsi?) cmos process, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt ultracmos? rf switch dc - 3000 mhz product description figure 1. functional diagram PE4210 features ? single 3-volt power supply ? low insertion loss: 0.30 db at 1000 mhz, 0.45 db at 2000 mhz ? high isolation of 35 db at 1000 mhz, 25 db at 2000 mhz ? typical input 1 db compression point of +14.5 dbm ? single-pin cmos or ttl logic control ? packaged in a small 8-lead msop notes: 1. device linearity will begin to degrade below 10 mhz. 2. the dc transient at the output of any port of the switch when the control voltage is switched from low to high or high to l ow in a 50 ? test set-up, measured with 1ns risetime pulses and 500 mhz bandwidth. table 1. electrical specifications @ +25 c, v dd = 3 v (z s = z l = 50 ? ) figure 2. package type
product specification PE4210 page 2 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0037-05 ultracmos? rfic solutions table 2. pin descriptions note 1: all rf pins must be dc blocked with an external series capacitor or held at 0 v dc . figure 3. pin configuration (top view) table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating in table 4. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 3. dc electrical specifications 4210 1 2 3 4 8 7 6 5 ctrl rfc gnd rf1 gnd v dd gnd rf2 table 5. control logic truth table absolute maximum rati ngs are those values listed in the above table. exceeding these values may cause permanent device damage. functional operation should be restricted to the limits in the dc electrical specifications table. exposure to absolute maximum ratings for extended periods may affect device reliability. pin no. pin name description 1 v dd nominal 3 v supply connection. a by- pass capacitor (100 pf) to the ground plane should be placed as close as pos- sible to the pin 2 ctrl cmos or ttl logic level: high = rfc to rf1 signal path low = rfc to rf2 signal path 3 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 4 rfc common rf port for switch (note 1) 5 rf2 rf2 port (note 1) 6 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 7 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 8 rf1 rf1 port (note 1) symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t op operating temperature range -40 85 c p in input power (50 ? ) 18 dbm v esd esd voltage (human body model) 200 v parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current (v dd = 3v, v cntl = 3) 250 500 na control voltage high 0.7x v dd v control voltage low 0.3x v dd v control voltage signal path ctrl = cmos or ttl high rfc to rf1 ctrl = cmos or ttl low rfc to rf2 control logic the control logic input pin (ctrl) is typically driven by a 3-volt cmos logic level signal, and has a threshold of 50% of v dd . for flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic high signal. (a minimal current will be sourced out of the v dd pin when the control logic input voltage level exceeds v dd .)
product specification PE4210 page 3 of 7 document no. 70-0037-05 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. evaluation kit the spdt switch evaluation kit board was designed to ease customer evaluation of the PE4210 spdt switch. the rf common port is connected through a 50 ? transmission line to the top left sma connector, j1. port 1 and port 2 are connected through 50 ? transmission lines to the top two sma connectors on the right side of the board, j3 and j4. a through transmission line connects sma connectors j6 and j8. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide model with a trace width of 0.030?, trace gaps of 0.007?, dielectric thickness of 0.028?, metal thickness of 0.0014? and r of 4.4. note that the predominate mode for these transmission lines is coplanar waveguide with a ground plane. j2 provides a means for controlling dc and digital inputs to the device. starting from the lower left pin, the second pin to the right (j2-3) is connected to the device ctrl input. the fourth pin to the right (j2-7) is connected to the device v dd input. a decoupling capacitor (100 pf) is provided on both ctrl and v dd traces. it is the responsibility of the customer to determine proper supply decoupling for their design application. removing these components from the evaluation board has not been shown to degrade rf performance. figure 4. evaluation board layout figure 5. evaluation board schematic peregrine specification 101/0037 peregrine specification 102/0035
product specification PE4210 page 4 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0037-05 ultracmos? rfic solutions typical performance data @ -40 c to 85 c (unless otherwise noted) figure 7. input 1 db compression point & iip3 figure 9. isolation ? rfc to rf1 figure 8. insertion loss ? rfc to rf2 figure 6. insertion loss ? rfc to rf1 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0 500 1000 1500 2000 2500 3000 insertion loss (db) frequency (mhz) -40 c 85 c 25 c 0 10 20 30 40 0 10 20 30 40 500 1000 1500 2000 2500 iip3 (dbm) 1 db compression point (dbm) frequency (mhz) iip3 1db compression -40 c 25 c -40 c 85 c 25 c -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 0 500 1000 1500 2000 2500 3000 insertion loss (db) frequency (mhz) -40 c 85 c 25 c -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 isolation (db) frequency (mhz) t = 25 c
product specification PE4210 page 5 of 7 document no. 70-0037-05 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. figure 11. isolation ? rf1 to rf2, rf2 to rf1 figure 13. return loss ? rf1, rf2 figure 12. return loss ? rfc to rf1, rf2 figure 10. isolation ? rfc to rf2 typical performance data @ 25 c -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 isolation (db) frequency (mhz) -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 isolation (db) frequency (mhz) rf1 rf2 -40 -30 -20 -10 0 0 500 1000 1500 2000 2500 3000 return loss (db) frequency (mhz) -40 -30 -20 -10 0 0 500 1000 1500 2000 2500 3000 return loss (db) frequency (mhz) rf1 rf2
product specification PE4210 page 6 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0037-05 ultracmos? rfic solutions 8-lead msop figure 14. package drawing table 6. ordering information front view 2.950.10 0.08 a b c 0.33 +0.07 -0.08 0.10 a 0.100.05 3.000.10 0.860.08 1.10 max - c - - a - 1 0.65bsc 0.510.13 2.450.10 0.510.13 2x 8 3.000.10 .25 a b c 234 - b - .525bsc top view 5 6 7 4.900.15 3.000.10 side view 2.950.10 order code part marking description package shipping method 4210-21 4210 PE4210-08msop-50a 8-lead msop 50 units / tube 4210-22 4210 PE4210-08msop-2000c 8-lead msop 2000 units / t&r 4210-00 PE4210-ek PE4210-08msop-ek evaluation kit 1 / box 4210-52 4210 PE4210g-08msop-2000c green 8-lead msop 2000 units / t&r 4210-51 4210 PE4210g-08msop-50a green 8-lead msop 50 units / tube
product specification PE4210 page 7 of 7 document no. 70-0037-05 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corp. 9450 carroll park drive san diego, ca 92121 tel 858-731-9400 fax 858-731-9499 north asia pacific peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213 europe peregrine semiconductor europe commercial products: batiment maine 13-15 rue des quatre vents f- 92380 garches, france tel: +33-1-47-41-91-73 fax : +33-1-47-41-91-73 space and defense products: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33(0) 4 4239 3361 fax: +33(0) 4 4239 7227 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos is a trademark of peregrine semiconductor corp. south asia pacific peregrine semiconductor 28g, times square, no. 500 zhangyang road, shanghai, 200122, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652
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